Intel® Pentium® II Xeon™ Processor Bus Terminator Design Guidelines

The Intel® Pentium® II Xeon™ processor includes termination circuitry for the microprocessor’s Assisted Gunning Transceiver Logic (AGTL+) bus. In a multiple-processor system each processor location (Slot 2 connector) must be properly terminated, whether or not all locations have processors installed. This document describes design considerations for a termination card to occupy unused connector locations and terminate the bus.

These design guidelines include layout rules and hints based on system design experience. They do not define a specific card design nor constitute a specification. Card designers will still need an understanding of the system the card will be used in, as well as the customary simulation and system testing. In the following four-way symmetric multi-processing (SMP) design example, all processor system bus AGTL+ signals are tied to +1.5V through a 150 W resistor, so that the bus maintains a 25 W impedance no matter what configuration is used in the five available slots. For a two-way SMP design (i.e. dual processor), the cluster controller connector is not needed. A two-way SMP design would simply have two processor locations and the 440GX AGPset or 450NX PCIset.

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