Microprocessor systems – lecture topics 2001/2002

  1. Microcomputer and microprocessor. Principles of von Neumann architecture. Arithmetical-logical unit. Accumulator, flags. Machine and command cycle. Addressing modes. Data exchange between the microprocessor and its environment: polling, interrupts, DMA. Devices addressing – separate I/O and memory-mapped I/O. Serial (synchronous and  asynchronous) and parallel transmission.
  2. Single-chip microcomputer 8051. Pins, basic machine cycles. Internal RAM. Special registers. ALU, flags. I/O ports. Buffering. Timer-counter unit.
  3. Single-chip microcomputer 8051. Serial port. Multiprocessor communication. Interrupts. Reset, low-power modes. Expanding the central unit: external program and data memories, I/O circuits, additional interrupts.
  4. Parallel I/O. How to simply organise a parallel transmission with acknowledgement. Universal register 8212. Programmable circuit 8255 – structure, operation modes, registers, programming, applications. Advanced functions of parallel I/O devices (selected properties of Z-80 PIO).
  5. Serial transmission circuits and timer-counters. Serial transmission circuit 8251 – structure, operation modes, registers, programming. Timer-counter unit 8253 – structure, operation modes, registers, programming.
  6. Interrupt controllers 8214, 8259 and 8259A – structure, operation modes, registers. Examples of daisy-chain and cascade connections. Cooperation with 8-bit and 16-bit microprocessors. DMA controllers 8257, 8237. Structure, operating modes, registers, programming. Advanced functions of DMA controllers (selected properties of Z-80 DMA).
  7. Modern microcontrollers. Harvard architecture - properties, advantages and disadvantages. PIC family microcontrollers - data and program memory organisation, addressing modes, interrrupt controller. AVR family microcontrollers - data and program memory organisation, addressing modes, interrrupt controller.
  8. Serial interfaces. Comparison of serial and parallel bus - advantages and disadvantages. Fundamental properties of I2C, SMBus, SPI, Microwire, 1-Wire.
  9. 8086 microprocessor. Structure – EU and BIU blocks. Registers, segmented memory organisation. Logical and physical addresses. Pins. Minimal and maximal operation modes. Memory organisation. Interrupts.
  10. Floating point coprocessor 8087. Co-operation with 8086. Data types. Internal registers.
  11. Microcomputers IBM PC/XT and PC/AT. Structure. ISA 8- and 16-bit buses.
  12. Microprocessor evolution from 8086 to 80486. Microprocessor 80286 – new properties, virtual mode addressing, co-operation with 80287 coprocessor. Microprocessor 80386 – new properties, virtual mode addressing, co-operation with 80287 or 80387 coprocessors.
  13. 80486 Microprocessor – architecture. Signals. Registers and flags. Logical and physical addresses. Segmentation – segment descriptors, descriptor registers. Paging – page directory structure, directory elements, TLB buffers.
  14. 80486 Microprocessor. Cache memory. Serial transfers. Write buffers. Task protection. Task state segment. System segments and gates descriptors. Interrupts and exceptions. Interrupt table in real and virtual mode.
  15. IBM PC Microcomputer – architecture development. EISA, MCA, VLB buses – basic properties. PCI bus. Structure of PCI bus equipped computer. PCI signals and cycles. Interrupts in PCI system
  16. PCI bus – configuration memory. Access to the configuration memory in IBM PC. Device classification. AGP bus – computer structure, signals, operation modes.
  17. Improving microprocessor efficiency. Pipelining. Superscalar microprocessor. Command dependencies solving. Branch prediction. BTB table, static and dynamic methods. Code optimisation. Cache – connection to the microprocessor, organisation. MESI protocol.
  18. Pentium and Pentium MMX microprocessors. Structure. Pipelining, instruction pairing. Cache. Pipelined FPU. MMX commands and data types.
  19. Pentium Pro, Pentium II, Pentium III microprocessors. Structure. RISC kernel operation. Instruction decoding. Reorder Buffer, Reservation Station, Memory Reorder Buffer. Execution units. L1 and  L2 cache. Command list enhancements and new data types – SSE, 3Dnow. Microprocessor identification.
  20. Modern memories. DRAM (SDRAM), DDRAM, RAMBUS
  21. Modern microprocessors. Intel Pentium 4, AMD Athlon. 64-bit architectures: VLIW, EPIC. Intel Itanium and AMD Hammer - a short comparison.

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